Patents and Publications

Product Acknowledgements & PeakView® Contributions

• • Q. Chen et al., “A single chain 800m/1.8g/2.4GHz Multistandard transceiver with multibranch transformer for low-cost IOT applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 12, pp. 4684–4688, Dec. 2022. doi:10.1109/tcsii.2022.3196434
  • Q. Liao et al., “A 50-GB/s pam-4 silicon-photonic transmitter incorporating lumped-segment MZM, distributed CMOS driver, and integrated CDR,” IEEE Journal of Solid-State Circuits, vol. 57, no. 3, pp. 767–780, Mar. 2022. doi:10.1109/jssc.2021.3134874
  • Y. Zhang et al., “A 23.6-38.3ghz low-noise PLL with digital ring oscillator and multi-ratio injection-locked dividers for millimeter-wave sensing,” 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 3–6, Aug. 2020. doi:10.1109/rfic49505.2020.9218347
  • X. You, H. Feng, X. Xing, and Z. Wang, “A power mixer based dual-band transmitter for Nb-IOT Applications,” 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 287–290, Aug. 2019. doi:10.1109/mwscas.2019.8884866
    
  • L. Rao, H. Feng, X. Xing, and Y. Tan, “A 15.6 dbm P, 24 DB gain, 24.4%PAE, linear CMOS power amplifier for 5G application,” 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 1–3, Jun. 2019. doi:10.1109/edssc.2019.8754295
  • B. Wheeler. (2019). Low Power, Crystal-Free Design for Monolithic Receivers. UC Berkeley. ProQuest ID: Wheeler_berkeley_0028E_18563. Merritt ID: ark:/13030/m5sr43cs.
  • X. Hu. (2019). Advanced on Chip-in-Cell Wireless Platform to Continuously Monitor Physiological Parameters in Single Cell. Stanford University. PhD Dissertation.
  • Raleigh Smith (2019). The Bang Bang PLL as a Clock Source in Serial-De-Serializer (SERDES) Applications. Carleton University. PhD Dissertation.
  • N. D. Saiz, G. Buckmaster, and T. H. Lee, “A ka-band Beamformer for wireless power transfer to Body Area Networks,” 2018 IEEE International Microwave Biomedical Conference (IMBioC), pp. 10–12, Jun. 2018. doi:10.1109/imbioc.2018.8428866
  • J. Han, N. Sutardja, Y. Lu, and E. Alon, “Design techniques for a 60-GB/s 288-MW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65-nm CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 52, no. 12, pp. 3474–3485, Dec. 2017. doi:10.1109/jssc.2017.2740268
  • F.-W. Kuo et al., “A bluetooth low-energy transceiver with 3.7-MW all-digital transmitter, 2.75-MW high-if discrete-time receiver, and Tx/RX Switchable on-Chip Matching Network,” IEEE Journal of Solid-State Circuits, vol. 52, no. 4, pp. 1144–1162, Apr. 2017. doi:10.1109/jssc.2017.2654322
  • H. Masnadi Shirazi et al., “On the design of MM-wave self-mixing-VCO architecture for high tuning-range and low phase noise,” IEEE Journal of Solid-State Circuits, vol. 51, no. 5, pp. 1210–1222, May 2016. doi:10.1109/jssc.2015.2511158
  • Qin et al., “A 5-GHz inductor-noise cancelling receiver with 1.8 DB noise figure in 65nm LP CMOS,” 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 83–86, May 2016. doi:10.1109/rfic.2016.7508256
  • Yan, L. Zhang, L. Zhang, and Y. Wang, “A 3.1–4.2 GHz automatic amplitude control loop VCO with constant KVCO and <10mv amplitude variation,” 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1654–1657, May 2016. doi:10.1109/iscas.2016.7538884
  • “Design techniques for a 60 gb/s 173 MW wireline receiver frontend in 65 nm CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 51, no. 4, pp. 871–880, Apr. 2016. doi:10.1109/jssc.2016.2519389
  • J. Luo, L. Zhang, L. Zhang, Y. Wang, and Z. Yu, “A 24ghz low power and low phase noise PLL frequency synthesizer with constant kvco for 60ghz wireless applications,” 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2840–2543, May 2015. doi:10.1109/iscas.2015.7169278
  • J. Charthad, M. J. Weber, T. C. Chang, and A. Arbabian, “A MM-sized implantable medical device (IMD) with ultrasonic power transfer and a hybrid bi-directional data link,” IEEE Journal of Solid-State Circuits, vol. 50, no. 8, pp. 1741–1753, Aug. 2015. doi:10.1109/jssc.2015.2427336
  • J. Luo et al., “A 64dB gain 60ghz receiver with 7.1DB noise figure for 802.11ad applications in 90nm CMOS,” 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2401–2404, May 2015. doi:10.1109/iscas.2015.7169168
  • J. Han, Y. Lu, N. Sutardja, K. Jung, and E. Alon, “A 60gb/s 173MW receiver frontend in 65NM CMOS technology,” 2015 Symposium on VLSI Circuits (VLSI Circuits), Jun. 2015. doi:10.1109/vlsic.2015.7231268
  • M. Taghivand, K. Aggarwal, Y. Rajavi, and A. S. Poon, “An energy harvesting 2×2 60 GHz transceiver with scalable data rate of 38–2450 MB/s for near-range communication,” IEEE Journal of Solid-State Circuits, vol. 50, no. 8, pp. 1889–1902, Aug. 2015. doi:10.1109/jssc.2015.2429716
  • M. Taghivand, K. Aggarwal, and A. S. Poon, “21.5 a 3.24-to-8.45GHz low-phase-noise mode-switching oscillator,” 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb. 2014. doi:10.1109/isscc.2014.6757473
  • Y. Han and J. Zhao, “Accurate substrate analysis based on a novel finite difference method via synchronization method on layered and adaptive meshing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 10, pp. 1520–1532, Oct. 2013. doi:10.1109/tcad.2013.2261437 
  • Y. Han and J. Zhao, “A novel high-capacity electromagnetic compression technique based on a direct matrix solution,” IEEE Transactions on Advanced Packaging, vol. 33, no. 4, pp. 787–793, Nov. 2010. doi:10.1109/tadvp.2010.2089788