PeakView EMD™ is a fast, 3D, full-wave and high-precision electromagnetic solver for on-chip passive device synthesis. EMD™ has an extensive synthesis library of parameterized devices aiding designers as they explore, design and adjust advanced components in preparation for circuit simulation and optimization.
In addition to a comprehensive standard library of passive device topologies, users have the flexibility to script customized PCircuits – parameterized EM devices – tailored to meet their specific design requirements.
EMD™ offers complete automation of the EM device synthesis flow through seamless integration of PeakView™ models into the Virtuoso® design environment. Ease and efficiency of EM design, combined with speed and high precision solver accuracy, provides a state-of-the-art EM solution for modern IC processes. EMD™ further facilitates electromagnetic analysis by including the PeakView PBM™ (Physics-based Model) feature that generates compact RLCK models preserving DC inductance and resistance.
EMD™ generates high quality EM data for passive devices that closely correlates to silicon measurements from major foundries and IC design companies.
- Full-wave EM Device Synthesis with a Standard Library and Extensibility
PeakView EMD™ provides full-wave EM device synthesis for advanced on-chip passive structures. The standard PCircuit library consists of a broad selection of parameterized devices, and is further extensible with Python code for user-defined devices.
- Accuracy, Performance and Capacity
PeakView’s patented EM solver combines high accuracy, computational performance and the capacity needed to analyze complex layouts with devices, interconnect and PCB interfaces.
- Physics-Based Modeling
A key benefit of working with EMD™ is the choice of using compact RLCK models for EM devices called Physics-Based models (PBM™). These circuit equivalent models are guaranteed to be passive and preserve DC inductance and resistance.
- Circuit and EM Co-Simulation
EMD™ provides a powerful feature for running circuit and EM Co-simulation driven from Virtuoso® Analog Design Environment (ADE). Users are able to sweep parameters of synthesized devices within ADE. PeakView™ computes the EM results and updates the simulation net-list for each iteration of the sweep.
With PeakView EMDTM, users have the choice to either: 1. instantiate a component from the standard PCircuit Library using a pull-down menu from the GUI, or, 2. import a customized PCircuit with user-defined geometry and design parameters that is scripted with Python. Example PCircuit geometries are shown in the following figure.
Example PCircuits: (a) customized symmetric multi-level inductor (b) line pairs with shield lines (c) customized bow-tie (d) patterned ground shield (PGS) (e) X-lines (f) guard ring (g) advanced balun (h) finger-caps
The values of parameter fields can be specified when a circuit is instantiated in EMD™. Or users have the option to perform a parameter sweep by entering a desired sweep range for a design variable. PeakView™ generates a family of child cells corresponding to each point in the range.
The following figure shows a group of curves generated by a PeakView™ sweep performed on the outer radius of an impedance matching transformer. Optimum design is achieved when transformer output impedance is: Z=200-60j at 2.4 GHz.
Another major feature of EMD™ is the capability to synthesize EM components with specified target values. PeakView electromagnetically analyzes all of the generated circuit topologies and automatically creates the necessary cell views. The generated views (i.e. schematic symbols, DRC clean layouts, S-parameter and Physics-Based models) are then synced to the Virtuoso® Design platform.
Advanced EM Modeling Features
1. PCircuit EM Device Synthesis
Users can choose from the standard PCircuit library consisting of a wide-ranging collection of sophisticated parameterized devices that includes inductors, baluns, transformers, transmission lines, capacitors and many other popular topologies. EMD™ also supports supplementary options to augment these components, i.e. patterned ground shields, guard rings, via fills etc., to achieve optimal design. Designers can refine and sweep design parameters and obtain accurate performance estimates from the powerful 3D EM solver.
Passive EM devices can also be synthesized to achieve a range of objectives. Users are able to specify design targets (e.g. inductance value) at certain frequencies, so that optimal designs are generated to match these physical parameters.
EMD™ offers full scripting flexibility with object-oriented Python code to extend the standard PCircuits to create customized passive devices. Customized PCircuits can be loaded into the PeakView GUI in order to perform full-wave EM simulation, synthesis and Virtuoso® layout generation.
2. CMP Support for Advanced Processes
EMD™ addresses sub-40nm challenges in advanced processes by using the PeakView™ chemical-mechanical polishing (CMP) option. This feature allows EMD™ to accurately simulate and extract complex wide metal slotting, staggered slotting/striping, and massive via arrays, aiding time-efficient, automated design. It provides comprehensive modeling methods to enable users to model dummy metal fill with their passive devices at all frequency ranges.
PeakView EMD™, in conjunction with CMP™, provides full support for advanced process node DFM requirements during EM synthesis and Layout EM extraction. Designers are able to define their own metal fill and slotting requirements in the PCircuit parameters. During EM synthesis, these rules are considered and PeakView delivers a DRC clean layout with the industry’s most accurate EM and circuit simulation models.
3. Physics-Based Modeling
In addition to purely numerical n-port S-parameter models, PeakView EMD™ provides the option to generate compact RLCK models that guarantee passivity and physical realizability. This option is known as the Physics-Based Modeling (PBM) solution. PBM generates EM models as Spectre or HSPICE compatible equivalent sub-circuits for use in transient circuit simulations. PBM models are guaranteed to be convergent and passive over a user selectable frequency range. PBM preserves the DC inductance and resistance and does not shift the circuit’s operating point. In addition, PBM automatically ensures the model to accurately take into account white noise content.
4. Foundry Adopted and Qualified
Lorentz Solution’s foundry user-base regularly utilizes the PeakView™ EM Design platform to design components for their reference flows in RF/AMS processes. PeakView™ is TSMC MS/RF RDK 2.0/3.0 qualified, and it has also established itself as an essential part of GLOBALFOUNDRIES’ AMS reference flow development. An example of a partial die with Peakview modeled inductors (DUTs) and test-keys for a TSMC 20nm process is shown in the figure. For each DUT, PeakView™ assigned different metal fill layers, densities and shapes. The test key structures are designed as open, short and through, useful for the post measurement processing such as de-embedding.
1. Circuit and EM Co-Simulation
EMD™ has a Circuit and EM Co-Simulation feature that can be driven from Virtuoso’s Analog Design Environment (ADE). Typically, circuit simulation and EM simulation are two different tasks. Designers use an EM simulation tool to generate a model for a device, and then manually transfer the model to a separate circuit simulation tool. If a parameter of the original device is altered, re-integration of the new model with the simulation tool is required for each new value. With the Co-simulation feature, EM simulation is driven by Circuit simulation in ADE and the device model is generated on the fly. Designers only need to consider the circuit level behavior, and EMD™ generates new device EM models and inserts the models into the net-list automatically. In this manner, users remain in the ADE environment, while PeakView™ handles the EM simulations in the background providing enhanced designer performance.
1. Customized Accuracy Types
In addition to pre-configured EM simulation types, PeakView™ has implemented Customized Accuracy Type to enhance the flexibility of accuracy settings and to configure layout processing and EM simulation options. By composing a configuration file, users are able to easily tune the tool such that the entire EM simulation process is optimized for special test cases. This is particularly useful for scenarios where concurrent simulation for structures of varying scales is required.
2. Multi-core Processing and Distributed Computing
In order to maximize utilization of computing resources, EMD™ takes advantage of PeakView’s multi-core processing capability. Design jobs can be run on compute farms consisting of multi-core machines, as well as on standalone platforms with multi-processor hardware. PeakView™ provides different distributed computing modes to concurrently accelerate the EM modeling. Users are able to specify different frequency points to be simulated on different machines in a compute farm for maximum efficiency of resources.
3. Hybrid Matrix De-composition Technology
PeakView™ has developed a hybrid matrix decomposition technology to achieve rapid solutions for both DC and EM simulation. A set of advanced mathematical methods which combines the advantageous aspects of sparse matrix and dense matrix solution technologies has been implemented in the engine. The overall simulation time is now greatly minimized with the new developments in matrix decomposition methodology.
Silicon Data Correlation
EMD™ simulations confirm excellent correlation to silicon data in advanced process nodes. It has been successfully deployed in characterizing a 20nm process node and verified within a 1-2% margin of error for inductance. A plot of silicon measurement vs. simulation for a single-ended total capacitance of a 1-turn inductor is shown in the following figure.
- EMD Setup
- iRCX format technology file from TSMC
- ITF format technology file from foundries
- EMD Input
- Standard Library PCircuit
- User-defined PCircuit
- EMD Output
- n-port, Physics-Based EM models.
- Cadence® library views, i.e. DRC clean layout, schematic symbols, etc.
- Linux 64 bit, i.e. Redhat and SUSE
- LSF-based computing farm