The needs for on-chip passive device and package co-simulation increase dramatically due to IC design trend in reducing the chip size, increasing the signal frequency, and stacking multiple chips in a package. IC designers need to take into account the overall EM effects from on-chip passive devices to the package balls as part of circuit design optimization. The mutual coupling between interconnects, bumps, and vias also play an important role to affect the circuit performance. It is desired to have a single EDA platform to serve IC designers for these needs.
The application of PeakView LEM has been expanded to package elements and board-level analysis. PeakView offers a convenient integration with chip design tools and package/board design tools, allowing users to skip the tedious configuration of traditional modeling tools and to achieve the truly optimized design by considering the whole physical environment in the critical region. Assisted by the innovative flexibility and solid accuracy of PeakView, designers can quickly assess the on-chip device performance after importing the package elements and PCB structures, which might be provided by other partners, to PeakView. Additionally, users can conduct the EM analysis of selected elements while the trivial periphery structures are automatically neglected.
The remarkably adaptive LEM efficiently handles the mix of on-chip/package/PCB structures such as on-chip inductor, bump, RDL/substrate routing, via, package ball, and PCB routing to generate a overall models that taking into account all the contributors. For example, vias produce discontinuity from the signal transition and significantly affect signal and power integrity in high speed designs. Parasitic capacitance of via can also increase signal rise time. The PeakView high capacity computation engine enlarges the computable dimensions to millimeter scale, but you can still get the most accurate model of the micron level on-chip devices.
Benefits of using PeakView On-Chip Packaging Co-simulation:
- A tool that is easy to setup and requires minimum EM expertise to use
- Optimized to handle special on-chip structures like via array
- Support and services such as design customization are available
- Shorten the design flow and make optimization of the whole design possible
EM Key Challenges: Vertical Inductance
For chip and package EM co-simulation, the vertical current through conductor and vias are important. Vertical inductance is notoriously difficult to capture including vertical inductance of vias, vertical inductance of thick metal, and all mutual coupling among vertical currents. PeakView overcomes this difficulty through rigorous vertical meshing and EM equations.
Bump Issues between IC/PKG and Peakview EM Modeling
While PDK includes layers only up to UBM (Under bump metal) and packaging tools include in PKG/PCB levels, solder ball (Bump) layers are not defined either in PDK or in packaging design tools. Without a special treatment, there is no connection between IC and PKG and vertical current bump effects will be missing.
Peakview has provided IC/PKG EM solution through incremental profile approach. This allows for TSV, UBM, BUMP and packaging layers EM co-sim with IC, and passivation opening and its setup in profile.
Visualization of the IC, Packaging and PCB Layers
PKG/PCB Import and Export Integration
1. Layout to PeakView using Cadence Virtuoso:
PeakView has been well integrated with Cadence Virtuoso. Users just need to click “Layout EM…” to transfer the layout data including pins to PeakView directly.
2. Layout to PeakView using GDS:
Users can easily stream in a GDS file into PeakView as a new cell. The “pin text file” records the name, layer and coordinates of all pins.
3. Layout to Peakview using ODB++:
PeakView supports importing design layouts using Virtuoso, GDS, and ODB++ formats. Users can transfer the layout data including pins to PeakView.
4. PKG/PCB Export ODB++ for 3rd Party EDA Co-simulation:
PeakView supports exporting design layout in ODB++ as well. It can be imported to true 3D EM simulator for system level simulation.