Cadence® and Custom Compiler™ Integration


PeakView™ is a full-wave, 3D electromagnetic design platform working directly from within an IC design environment. Its interactive GUI is seamlessly integrated with the Cadence® Virtuoso® and Custom Compiler™ layout editors. PeakView™ is a self-contained software suite that provides an EM solver, critical components of high-frequency modeling, parameterized passive device synthesis and advanced process node support for addressing DFM requirements.

PeakView™ products are launched from the menu bars of IC layout editors. Its synthesis and modeling framework provide optimal devices and automatically creates all of the required design library views. The generated views include EM models ready for circuit simulation, top-level test-schematics, layouts and symbols of the designs.

PeakView™ Integration with Virtuoso® Design Environment

PeakView™ Integration with Custom Compiler™ Design Environment

Circuit and EM Co-Simulation

PeakView™ provides a powerful feature to run circuit and EM Co-simulation driven from Virtuoso® Analog Design Environment (ADE). Users are able to sweep parameters of synthesized devices from within ADE.  PeakView™ computes the EM results and updates the simulation net-list for each iteration of the sweep. Designers only need to consider the circuit level behaviour, and PeakView™ generates new device EM models and inserts the models into the net-list automatically. In this manner, users remain in the ADE environment, while PeakView™ handles the EM simulations in the background providing enhanced circuit optimization and chip design performance.

Layout EM Extraction

PeakView LEM™ structural simulation and extraction solution provides users with a fast, easy to use, 3D EM modeling capability from within their design environment. A single click from the Virtuoso® layout views allows for any design with passive structures and interconnect to be automatically extracted for a complete 3D electromagnetic analysis.

Support for Hierarchy Editor

All PeakView™ generated cell-views that are synced to the design library can be selected for circuit simulation using the Cadence® Hierarchy Editor. The range of cell-views to select from includes process corner and temperature coefficient analysis models. PeakView™ generates S-parameter and lumped models that account for process corner and temperature sweeps (For instance, foundries provide several types of technology files in terms of Rbest, Rworst etc. that reflect process variation. Temperature co-efficients of materials are also obtained from technology files). These models can then be selected for circuit simulation using the Hierarchy Editor or device property in the schematic view.

Interconnect Analysis

PeakView HFDTM is integrated into Virtuoso® schematic and layout editors and customary RC extraction flows, enabling designers to work within a familiar IC design environment. Designers select nets from the schematic or layout editor and HFD then prepares them for coupling analysis. HFD manages all of the details behind the scenes and automatically ensures design data integrity while including the effects of EM coupling in circuit simulations.

Supported Cadence Virtuoso Versions

PeakView EM Design Platform runs on Cadence supported versions of Virtuoso including 5.x and 6.x. Support databases include both OpenAccess (OA) and CDBA.

Synopsys Custom Compiler Integration and Supported Versions

PeakView EM Design platform (EM Synthesis and Simulation) has been integrated with Synopsys Custom Compiler. Designers using Custom Compiler can conveniently use PeakView (EM, LEM) features. PeakView EM Design Platform runs on Synopsys supported versions of Custom Compiler including 17.x and 19.x. Support databases include OpenAccess (OA).

PeakView also supports the netlisting intercompatibility between the Virtuoso and Custom Compiler.


Comments are closed.