Latest PeakView™ Version: 4.2.6
Release Date: 10/02/2019
Enhancements and New Features in 4.2.6:
EM Quality and Layout Processing
- We continue to improve memory efficiency and performance of the computational engine, and observe up to 30% memory reduction in matrix building stage (P’LP) for a test case with Quick EM setup and ignore capacitance. For a certain testcase with 290K unknowns, using QuickEM, resereved memory reduced from 60GB to 41.3GB in this version.
- The matrix formation time for simulations has been further reduced by 5-10%.
- The solver can be now accelerated by about 30% at the cost of 2×memory, by using regular Bunch-Kaufman solver instead of the packed one. For now, this option is not turned on by default.
Design Automation and Design Environemnt Integration
- In this release, we introduce a new feature, Advanced LEM, to allow users to pre-process layout before transferring the layout to PeakView. This powerful new feature is based on SKILL code, and the user can create and load their own customized Layout EM (LEM) function as well. To enable the Advanced LEM feature, users need to add the option into .peakviewinit file: option.peakview_load_list += [“NTN.il”, “PKG.il”, …], where “NTN.il”, “PKG.il”, … are the paths to SKILL files. This will add new options under “PkView” menu tab in Cadence Layout window.
- Also, the user has control on the synced-back-to-Virtuoso outcome of Advanced LEM cell; the synced-back cell can either be in the new “Cell” or in the new “View” of the same cell.
- Improve the feature of parameter sweeping with supercell in ADE-XL so that parameter sweeping process will not be interrupted by popped up error
message. Previously, the error message would pop up if the device layout was invalid in PeakView and halted supercell parameter sweep.
- Now we support log/replay function for profile conversion.
- Enhanced netlisting procedure has been introduced for PeakView in Custom Compiler. The user can change the interpolation type in Custom Compiler now, and also fmax is set automatically.
- In this release, we provide a new built-in parser to generate profile directly from ICT format tech file. This improves PeakView’s capability of adapting to the various developing semiconductor fabrication technologies and process information.
- In this release, we introduce a new incremental profile with section name “SUBLAYER” to allow users to add conductive region in the substrate area. This gives more flexibility to users who might want to investigate the effects of substrate layers, such as epi-layer or nwell/pwell region.
High Frequency Design (HFD)
- In this release, HFD GUI has been improved to not show in Nets/Device list the net(s) existing in layout but not schematic. This prevents the user(s) from selecting them during Group creation and seeing the error(s) in back annotation.
- Also, we redesign HFD GUI to make it more clean, flexible and powerful. First, we add EM setting into HFD GUI, now user can directly do EM setting for HFD groups there. Second, we allow a user to do Layer Range setup (right-click menu -> “HFD Option… ”-> “Layer Range”) for the individual group rather than one setting for all groups. Finally, we rearranged HFD GUI buttons for user easy to follow.
- PeakView will now remember the Chart windows that were open when users save their project.
- The simulation log now displays more details about data preparation stages for EM engine.
- For user’s convenience, EM Post-Processing GUI display has been further improved to explicitly display at the bottom the pins that have been assigned
as default pin type. (Star sign “*” is used to indicate the default pin type, and any pin that is not specified in any file will be assigned as that default type) .