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Industry’s Most Powerful Electromagnetic Design Platform that guarantees the best “Accuracy, Speed and Capacity” 

The PeakView EM design platform offers a comprehensive total solutions to drastically simplifies the challenge and complexity for today’s high frequency semiconductor designs. PeakView™ is process independent, we offer a complete set of passive devices for synthesis and customization at any process technologies. Our powerful LEM™ (Layout EM) performs 3D full wave EM simulation and modeling within the IC design environment. Our unique EM Prototyping™ and HFD™ (High Frequency Designer) enables EM design, coupling and interconnect analysis that readies for mmWave-THz frequencies. We also guarantee passivity for S-parameter models with their corresponding PBM™ (Physics-Based Models) or compact RLCK models that support transient circuit simulation. High quality EM data generated from PeakView™ demonstrated close correlation to silicon measurements. Our user-friendly and world-class support bears the hallmark of integrity and excellence.  



Lorentz Solution, Inc. presents the PeakView™ electromagnetic design platform providing users with a fast, automated, IC design experience. The state-of-the-art software suite, along with a 3D full-wave EM solver at its core, radically revolutionize the process of high frequency semiconductor design with confidence from prototyping to sign off.


Layout EM provides 3D full wave EM simulation for as-is layout with DC – mmWave – TeraHertz accuracy and huge capacity in foundry PDK environment.


Fullwave 3D EM synthesis and optimization in multi-project PDK environment with comprehensive process-independent passive device pcircuit library.


Circuit-level EM isolation, coupling and crosstalk modeling and simulation throughout design stages and before LVS clean.                                           


PLX is Peakview’s Parasitic Inductance Extraction feature which complement todays RC extraction flow by extracting and modeling the parasitic inductance of interconnect then back-annotate to the RC network in DSPF file.


Circuit-level LVS/LPE based interconnect/passive EM analysis/extraction/back annotation, extending mainstream RC flow, for analog, RF and mmWave design sign-off.


Simulation of 3DIC and Chip-Package-PCB designs with foundry PDK-based profile and incremental packaging profile, with simplified and reliable methodology.




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