PeakView Chip/Packaging EM Co-Simulation™

Overview

We have developed a user-friendly, novel utility Chip/Packaging EM Co- Simulation™ equipped for IC, package, and board-level electromagnetic coupling analysis. The utility expands the application of PeakView LEM™ to include package and PCB signal integrity analysis. This feature provides an efficient solution to address EM design challenges concerning chip-to-board and chip-to-package interactions. It resolves key issues underlying system-level design and verification and provides a fast, accurate, and easy-to-use EM solution in a simplified user interface.

IC/PKG EM Co-Sim™ aligns reference co-ordinates (relative positioning of board/IC/package) to account for scale and unit differences. It provides an accurate EM model of vertical paths that account for series and shunt inductance, shunt capacitance, and skin effects.

Benefits

  • PCB Impedance Analysis

At high frequencies, as noise currents and electromagnetic coupling to PCB traces increase, signal integrity issues and potential power delivery problems need to be identified earlier on in PCB designs. A full-system, EM analysis is necessary to examine the frequency-dependent impedances in the supply paths and to determine the placement of sensitive circuitry on the board. Few integrated tools are available that provide an easy-to-use, accurate EM solver for IC designers. In most cases, only experts in electromagnetic phenomena are able to make efficient utilization of these tools.

IC/PKG EM Co-Sim™, with an accurate PCB impedance analysis, assists designers to:

  1. Minimize unintended radiation caused by loop currents through ground return paths.
  2. Minimize noise in high impedance power distribution networks, where noise-level is proportional to the currents.
  3. Obtain frequency response of the total circuit, which is influenced by the serial impedance effects along a signal path.
  4. Ensure stability of the AC reference, since impedances on the AC ground is impacted by PCB design.
  5. Reduce ground bounces due to high- speed IC switching events that introduce an element of unpredictability to the circuit characteristics.
  • Layout Processing for Co-existing Package and On-chip Elements

Simultaneous simulation of co-existing package structures and on-chip devices warrant sophisticated CAD geometry processing capabilities. Devices (e.g. on-chip passives) and package elements (e.g. via pillars, solder bumps) vary markedly in size. Typical on-chip inductors are in the order of 100u in radius, 10u in line-width, and less than 5u in thickness, while packaging structures are usually several mm in length, 100u in line-width and more than 20u in thickness.

IC/PKG EM Co-Sim™ provides a full-system analysis of all components of varying scales with accurate meshing. The tool has the computational capacity for very large solution spaces (multi-layer PCBs, for instance).

  • Meshing Circular Paths and Via Holes

Unlike devices with straight-line or polygonal contours, packaging structures often contain circular geometry or arbitrary curly shapes. Vertical paths also contribute to significant reactive effects and must be modeled correctly. The meshing of circular paths and holes are given specialized consideration to obtain an optimal balance in accuracy and computing cost. 

  •  High-speed Switching

Spurious electromagnetic emissions can arise from high-speed CMOS switching circuits or current impulses from clock signals through gates. The average current and spectrum depend on the switching frequency. IC/PKG EM Co-Sim is able to examine these events in transient circuit simulations with numerically convergent, passive PBM models.

IC/PKG EM Co-Simulation™ Features

Advanced EM Modeling Features

1.   Simple Incremental Profile Approach

The metal stack information of IC and packaging layers are different. PeakView™ has incorporated an ‘Incremental Profile’ approach. Instead of modifying the base profile, the incremental profile is just an add-on to that which is based on specific packaging needs. This feature is particularly important as nowadays, all of the advanced node profiles are encrypted. In this approach, the original IC profile file remains unchanged. 

2.   Large-Capacity Solution Space

The PeakView™ IC/PKG EM Co-Sim utility is built as an extension to our current LEM (Layout EM) feature. The board-level solution has the computational power to handle electromagnetic problems that would otherwise require memory in the order of (Terabytes) TBs.

PCircuitSPICE Simulation-ready PeakView™ Models for PCB Traces

PeakView™ uses GDS data transfers for full-board simulation with multi-layer PCBs. Applications include placement of sensitive magnetic sensors in optimum PCB locations that ensure minimal board impact.

In our present capability, the Peakview™ 3D solver obtains board-level input from PCB design tools (i.e. Cadence® Allegro®) and generates a SPICE simulation-ready model in a very short time.

3.  Simplified Layout Processing

IC/PKG EM Co-Sim™ processes PCB geometry generated by Cadence® Allegro® in .gds file format and generates a corresponding layout for full-wave simulation.

PCircuitBoard-level Analysis using IC/PKG EM Co-Simulation™

The layout is algorithmically verified and modeled; users are not required to make any modification or simplification to their designs. PeakView™ uses efficient strategies to handle PCB and packaging layouts without compromising simulation accuracy.

4.   EM Solver Capability for On-Chip and Packaging Structure

A combined on-chip and packaging structure require separate EM simulation settings for a substantial EM modeling: dense mesh for on-chip structure and coarse mesh for packaging structure. PeakView IC/PKG EM Co-Sim feature is compliant to initiate required settings. 

5.   Meshing

Advanced meshing algorithms are used to preserve details of circular or atypical contours in boards and planar elements in the design.  The meshing mechanism provides scale-specific processing of on-chip and package-level structures. Vias, polygons, curved surfaces, and intersections are optimally meshed and quickly solved by the simulation engine.  

 

Tool Integration

1.   Allegro Interface

PeakView™ is able to directly import layouts in .gds format (in the event Allegro® is used as a standalone tool).  Alternatively, if Virtuoso® Layout Editor is used to invoke Allegro®, then PeakView™ is also able to utilize this interface as a data exchange channel. In the latter case, Peakview LEM™ can be launched from the Virtuoso® IC environment to analyze the layout created initially using Allegro®. All the pins will be loaded automatically which is helpful as the packaging structure contains hundreds of ports.

2.  ODB++ Interface

ODB++ provides an intelligent, single data-structure for PCB design, including features, vias, pins, etc. It has been widely used by PCB design and manufacturing organizations.

PeakView™ is able to import ODB++ format which supports by most of the 3rd party PCB/package design tools. Users can easily import geometries from their desired PCB/packaged design tools to PeakView including automatic loading of all the pins for EM simulation. PeakView™ is also able to export the ODB++ format. It can then be imported to a true 3D EM simulator, such as Ansys, AWR, CST, etc, for system-level simulation.

High-Performance Features

1.   Customized Accuracy Types

Customized Simulation Type is a feature implemented to enhance the flexibility of PeakView™ and to allow users to configure layout processing and simulation options in addition to pre-configured EM simulation types. By composing a configuration file, users are able to easily tune the tool such that the entire EM analysis process is optimized for special test cases. This feature is required for concurrent simulation for structures of varying scales in the chip-package co-design. 

2. EM Key Challenges

For IC/PKG EM Co-Simulation, the vertical current through conductors and vias are important. 

  • Vertical inductance (including mutual vertical inductance) is difficult to capture.
  • Vertical inductance of vias
  • Vertical inductance of thick metal
  • All the coupling among vertical currents.

Using rigorous vertical meshing and EM equations, PeakView effectively captures vertical inductance, vertical resistance as well as sidewall capacitance of vias and thick metals.

Field Visualization of Vertical Inductance of Via-Metal Stack

IC/PKG EM Co-Simulation™ Flow

The PeakView IC/PKG EM Co-SimTM flow enables users to import structure layout into PeakView using Virtuoso, GDS, or ODB++ methods. Design layouts that contain compound structures of varying scales (on-chip devices, large RDL lines, PCBs, planar package elements) and contours (polygons of any angles, circular via holes, curved paths) are accurately processed by LEM™.

IC/PKG EM Co-Sim™ generates a corresponding layout in the PeakView™ GUI based on the imported information. The add-on incremental profile that contains the packaging layer information leaves the IC profile unchanged. PeakView’s high precision EM engine is then used to electromagnetically analyze the layout and create relevant views corresponding to the EM models. Generated views are then synced to the Virtuoso® Library to be used for SPICE simulation.

PKG Flow

Supported Formats

  • IC/PKG EM Co-Sim Setup
    1. iRCX format technology file from TSMC
    2. ITF format technology file from foundries
  • IC/PKG EM Co-Sim Input
    1. GDSII format layout generated by Cadence® Allegro® or other tools.
    2. ODB++ Import
  • IC/PKG EM Co-Sim Output
    1. n-port, Physics-Based EM models.
    2. Model views added to Cadence® Library.
    3. ODB++ Export
  • Platform
    1. Linux 64 bit, i.e. Redhat and SUSE
    2. LSF-based computing farm

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