On-Chip Packaging Co-simulation

Peakview has the capability to run on-chip packaging structure modeling to avoid tedious design flow in Allegro and HFSS.


Benefits of using PeakView On-Chip Packaging Co-simulation:

A tool that is easy to setup and requires minimum EM expertise to use

Optimized to handle special on-chip structures like via array

Support and services such as design customization are available

Shorten the design flow and make optimization of the whole design possible


The planar structure in PCB + package

Metal layers may be directly stacked without vias in between, and vice versa.

Layer Boolean operation which generates certain virtual layers profile can perfectly resolve this issue.



PeakView has been integrated with Cadence Virtuoso. Users can transfer the layout data including pins to PeakView. Users can stream in a GDS file and get a new cell. They can import ODB++ to Peakview.




Embed PeakView exported ODB++ of passive device to package/PCB level for system simulation



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