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The High-Frequency Design Gap
Designers of today’s high-frequency chips are facing unprecedented market pressures to innovate and find ways to achieve faster signal rates and overall bandwidths. High-performance digital clocks systems requiring greater than 3 GHz operating frequencies are burdened by the networks inherent capacitive coupling. Designers of high-speed analog applications, such as SerDes, using differential signaling techniques are seeking better ways to extend bandwidth beyond what is required for 40 Gbit Ethernet chips. And of course, the markets thirst for cost-effective multimode, multi-band single chip radios has RF design teams scrambling to find better ways to deliver new wireless products with more features and capabilities inside 6-9 month market windows. It will be these types of chip designs that will find their way into the next wave of high-volume price-sensitive commercial “killer applications” that will help drive the electronics industry going forward. Unfortunately, today a significant high-frequency “design gap” exists that inhibits design teams from delivering these types of chips on-time with competitive die sizes.
EM Design & Verification
Today’s advanced RFIC designs require more accurate circuit simulations than ever before. Designer’s now require EM-accurate models for on-chip passive devices and critical interconnect. Going forward, designer’s must increase the amount of EM simulation and modeling required to adequately characterize stray electrical parasitics induced by EM inductive and capacitive coupling. Most design methods today address on-chip EM coupling through excessive over design measures that usually result in larger than necessary die sizes. These design flaws are called EM Integrity design faults and when unaccounted by the designer lead to lost performance and costly silicon re-spins. For many design teams the time has come to extend their existing design practices to dramatically increase the amount of EM design & verification required to achieve final sign-off.
A New EM Design Practice is Needed
In order to bridge he aforementioned design gap, designer’s must regain control over the design of on-chip passive devices and eliminate EM coupling effects that leads to inefficient die utilization and significant performance loss often resulting in hard silicon failures and costly redesign.
What is needed is a new IC-focused EM design and verification design practice. One that complements existing design tools, methods, and procedures by seamlessly integrating Full-Wave EM simulation of passive devices and coupling parasitic effects into standard design flows utilizing popular circuit design, simulation, and layout and verification toolsets. Such an EM design practice would emphasize the need to “design for” and continuously “verify” interconnect and substrate coupling parasitic effects throughout the entire design flow.
Of particular interest is the design and modeling of on-chip inductors where precisely determining the proper geometric layout to yield exact inductance (L) values and quality factor (Q) necessary to achieve critical design goals remains somewhat of a black art. The designs of these passive structures have long been considered by design teams as part of their “secret sauce” used to competitively differentiate their LNA, VCO and filter implementations treating the resulting inductor architectures and layouts as critical company intellectual property.
However, to develop and deploy a competitive EM design practice has its own set of challenges. First and foremost is the scarcity of design engineers with adequate EM semiconductor experience. Secondly, most companies lack the extensive (and increasingly expensive) test chip development experience required to prove out innovative device architectures and to devise layout rules that deliver “coupling-free” implementations with the smallest footprint. Next, today’s general purpose EM simulation tools are poorly integrated and are designer unfriendly requiring extensive EM knowledge and training to be effectively used. In addition, these general purpose EM tools commonly require very long simulation times (many hours to days) to generate a result making them impractical as design tools. Lastly, the design, layout and modeling of sub-65nm inductors has become extremely complex and must now address new chemical-mechanical polishing (CMP) requirements that includes slotting of wide metals and dummy metal fill.
Lorentz Solution
Lorentz has a better solution! PeakView, the company’s EM Design and Verification platform has been architected from the ground up to be used by designers to improve and extend their EM design practices. Now high-frequency circuit designers and layout teams alike can optimize circuits for EM effects by quickly and confidently exploring many different implementations leading to higher performing circuits with a much smaller chip area.
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