The weak link today in high speed analog and RF circuit design is interconnect. At present, designers rely on RC extraction and ignore inductive effects, or they painstakingly extricate interconnect elements for separate analysis, then try to re-integrate the results back in their circuit for simulation.
Neither one of these approaches works for reasons designers know all too well:
- Double counting
- High pin counts
- Complicated layout traversing many level and layers
- Command line interfaces
- Complicated tool set up
- Poor quality EM analysis
- Bloated models
- Human error
Lorentz set out to change this with a new approach – PeakView High Frequency Designer (HFD). The requirements for the solution to this problem are:
- Automatic net isolation from layout
- Tight integration with the LVS/LPE flow
- Unparalleled EM accuracy
- Back annotation to circuit simulation view
- Results that are ready for transient circuit simulation
A field-solver point tool is not enough. An EM design platform, with advanced features, flow integration and state of the art modeling capabilities is what Lorentz used to create this solution
But even then many technical hurdles needed to be overcome. We have added a new modeling feature that allows any interconnect to be modeled for transient simulation. We worked with Mentor Graphics to use Calibre in a novel way to make the integration much easier for designers to use. This coupled with PeakView’s widely recognized Virtuoso and ADE integration makes a complete system for analog circuit design closure.
We have demonstrated this flow on RF Reference Designs from TSMC and have validated that the results match silicon at 40 to 60 GHz. We have also worked closely with Stanford University who developed silicon fabricated at TSMC running at over 60GHz to show that HFD results correlate well. Our major customers are using the HFD flow to ensure first time silicon, improve yield success and build better products that help millions of people communicate every day.