We have developed a user-friendly, novel utility PkPCB™ equipped for IC, package and board-level electromagnetic coupling analysis. The utility expands the application of PeakView LEM™ to include package and PCB signal integrity analysis. This feature provides an efficient solution to address EM design challenges concerning chip-to-board and chip-to-package interactions. It resolves key issues underlying system-level design and verification, and provides a fast, accurate and easy-to-use EM solution in a simplified user interface.
PkPCB™ aligns reference co-ordinates (relative positioning of board/package/IC) to account for scale and unit differences. It provides an accurate EM model of vertical paths that account for series and shunt inductance, shunt capacitance and skin effects.
- PCB Impedance Analysis
At high frequencies, as noise currents and electromagnetic coupling to PCB traces increase, signal integrity issues and potential power delivery problems need to be identified earlier on in PCB designs. A full-system, EM analysis is necessary to examine the frequency-dependent impedances in the supply paths and to determine the placement of sensitive circuitry on the board. Few integrated tools are available that provide an easy-to-use, accurate EM solver for IC designers. In most cases, only experts in electromagnetic phenomena are able to make efficient utilization of these tools.
PkPCB™, with an accurate PCB impedance analysis assists designers to:
- Minimize unintended radiation caused by loop currents through ground return paths.
- Minimize noise in high impedance power distribution networks, where noise-level is proportional to the currents.
- Obtain frequency response of the total circuit, which is influenced by the serial impedance effects along a signal path.
- Ensure stability of the AC reference, since impedances on the AC ground is impacted by PCB design.
- Reduce ground bounces due to high- speed IC switching events that introduce an element of unpredictability to the circuit characteristics.
- Layout Processing for Co-existing Package and On-chip Elements
Simultaneous simulation of co-existing package structures and on-chip devices warrant sophisticated CAD geometry processing capabilities. Devices (e.g. on-chip passives) and package elements (e.g. via pillars, solder bumps) vary markedly in size. Typical on-chip inductors are in the order of 100u in radius, 10u in line-width and less than 5u in thickness, while packaging structures are usually several mm in length, 100u in line-width and more than 20u in thickness.
PkPCB™ provides a full-system analysis of all components of varying scales with accurate meshing. The tool has the computational capacity for very large solution spaces (multi-layer PCBs, for instance).
- Meshing Circular Paths and Via Holes
Unlike devices with straight-line or polygonal contours, packaging structures often contain circular geometry or arbitrary curly shapes. Vertical paths also contribute to significant reactive effects and must be modeled correctly. The meshing of circular paths and holes are given specialized consideration to obtain an optimal balance in accuracy and computing cost.
- High-speed Switching
Spurious electromagnetic emissions can arise from high-speed CMOS switching circuits or current impulses from clock signals through gates. The average current and spectrum depends on the switching frequency. PkPCB is able to examine these events in transient circuit simulations with numerically convergent, passive PBM models.
Advanced EM Modeling Features
Advanced meshing algorithms are used to preserve details of circular or atypical contours in boards and planar elements in the design. The meshing mechanism provides scale-specific processing of on-chip and package-level structures. Vias, polygons, curved surfaces and intersections are optimally meshed and quickly solved by the simulation engine.
2. Large-Capacity Solution Space
The PeakView™ PCB utility is built as an extension to our current LEM (Layout EM) feature. The board-level solution has the computational power to handle electromagnetic problems that would otherwise require memory in the order of (Terabytes) TBs.
PeakView™ uses GDS data transfers for full-board simulation with multi-layer PCBs. Applications include placement of sensitive magnetic sensors in optimum PCB locations that ensure minimal board impact.
In our present capability, the Peakview™ 3D solver obtains board-level input from PCB design tools (i.e. Cadence® Allegro®) and generates a SPICE simulation-ready model in a very short time.
3. Simplified Layout Processing
PkPCB™ processes PCB geometry generated by Cadence® Allegro® in .GDS file format and generates a corresponding layout for full-wave simulation.
The layout is algorithmically verified and modeled; users are not required to make any modification or simplification to their designs. PeakView™ uses efficient strategies to handle PCB and packaging layouts without compromising simulation accuracy.
1. Allegro Interface
PeakView™ is able to directly import layouts in .GDS format (in the event Allegro® is used as a standalone tool). Alternatively, if Virtuoso® Layout Editor is used to invoke Allegro®, then PeakView™ is also able to utilize this interface as a data exchange channel. In the latter case, Peakview LEM™ can be launched from the Virtuoso® IC environment to analyze the layout created initially using Allegro®.
1. Customized Accuracy Types
Customized Simulation Type is a feature implemented to enhance the flexibility of PeakView™ and to allow users to configure layout processing and simulation options in addition to pre-configured EM simulation types. By composing a configuration file, users are able to easily tune the tool such that the entire EM analysis process is optimized for special test cases. This feature is required for concurrent simulation for structures of varying scales in the chip-package co-design.
2. Hybrid Matrix De-composition Technology
PeakView™ has developed a hybrid matrix decomposition technology to achieve rapid solutions for both DC and EM simulation. A set of advanced mathematical methods which combines the advantageous aspects of sparse matrix and dense matrix solution technologies has been implemented in the engine. The overall simulation time is now greatly minimized with the new developments in matrix decomposition methodology.
The PeakView PkPCBTM flow enables users to first import a GDSII format PCB layout into their Virtuoso® environment. Then LEM™ is invoked to export this layout to PeakView for running EM simulation.
Design layouts that contain compound structures of varying scales (on-chip devices, large RDL lines, PCBs, planar package elements) and contours (polygons of any angles, circular via holes, curved paths) are accurately processed by LEM™.
PkPCB™ generates a corresponding layout in the PeakView™ GUI. PeakView’s high precision EM engine is then used to electromagnetically analyze the layout and create relevant views corresponding to the EM models. Generated views are then synced to the Virtuoso® Library to be used for SPICE simulation.
- PkPCB Setup
- iRCX format technology file from TSMC
- ITF format technology file from foundries
- PkPCB Input
- GDSII format layout generated by Cadence® Allegro® or other tools.
- PkPCB Output
- n-port, Physics-Based EM models.
- Model views added to Cadence® Library.
- Linux 64 bit, i.e. Redhat and SUSE
- LSF-based computing farm