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Introducing PeakView
Today’s advanced High-Frequency (HF) IC designs require more EM design and verification than ever before. HF designs are especially susceptible to on-chip electromagnetic (EM) inductive and capacitive coupling effects that degrades circuit signal integrity and overall design performance. Detecting EM Integrity design faults early enables designers to take corrective action and compensate for these coupling effects . PeakView from Lorentz Solution, Inc., is the industry’s first IC-focused EM Design & Verification Tool Suite intended to accelerate EM Integrity design closure. PeakView comes modularly packaged providing design teams flexibility to tailor configurations to meet their specific requirements and can scale to meet their future needs. PeakView delivers a flexible set of high-capacity, high-accuracy full wave 3D EM Synthesis and Simulation capabilities to users of the Cadence IC design environment.
PeakView’s EM Engine typically runs 100X faster than other general purpose full-wave solvers and has repeatedly demonstrated results that match silicon measurements. Using PeakView, designers confidently capture EM coupling effects directly from layout and pass this information onto SpectreRF for circuit simulation. The tool suite includes fast & accurate EM device design & synthesis that automates the layout, model generation, and manages all the necessary Cadence design Views (symbol, schematic, layout…) making PDK and design flow integration a snap! PeakView’s passive broadband modeling engine bridges the S-parameter to circuit modeling gap by automatically converting S-parameter models into an equivalent subcircuit model for circuit simulation. PeakView’s layout extraction engine provides the industry’s first “1-click” layout extraction and full wave EM simulation of complex passive layout structures directly from the Cadence custom IC layout environment. Now even complex passive layout structures can be readily analyzed for EM coupling impact without leaving the preferred layout environment. PeakView has been outfitted to handle emerging Chemical-mechanical polishing (CMP) requirements of sub-90nm process technologies. Wide metal slotting/striping and dummy metal fill requirements are satisfied during EM synthesis and are accurately extracted and modeled as part of layout EM extraction. These types of structures have proven to be too complex to layout manually and too challenging for general purpose EM solvers to address without extensive simplification that compromises accuracy beyond usefulness.
Leading edge RF design companies have chosen PeakView to extend their competitive advantages by delivering a complete EM design practice to their designers desktops. Their designers have regained control over passive device and sensitive interconnect design leading to on-time project deliveries and higher performing circuits. Isn’t it time to upgrade your EM design practice too?
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