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Most EM Design Practices in place today have an inherit EM design throughput bottleneck. It takes too long to transform design-specific device specifications into real physical layouts and produce an accurate EM model for circuit design purposes. The demand for design-specific devices is steadily increasing as more design teams are added and/or the number of on-chip passives per design increases. As a result, only a limited number of EM device design iterations geared towards circuit optimization and tuning can be accomplished during any one design cycle. Each EM design pass can take several days to several weeks! That’s too long! At risk is missed project schedules, silicon re-spins to fix EM Integrity design flaws, and falling short of target performance objectives. What is needed is a new approach to EM Design that returns control of on-chip passives back to the design engineer.
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